P8X32A Emulation on FPGA Boards ——————————- The Propeller 1 Design is a collection of Verilog and AHDL source files that describes the hardware of the Parallax Propeller 1 microcontroller. This source can be compiled and downloaded to a compatible FPGA development board to emulate the Propeller 1 hardware. In fact, this is how the Propeller 1 was designed and tested before silicon was produced.
With this project, you can run our Propeller 1 design and experiment with modifications in the Verilog hardware description language right on your own workbench.
If you’ve ever wondered how the Propeller chip actually works, it’s all in front of you now, and it is malleable.
All files provided are Copyright 2014 Parallax Inc. and distributed under the GNU General Public License v3.0. A copy of this license is included with the files of this repository. The GPL license grants end users the freedom to use and modify the software provided it is copylefted to ensure that any derived works are distributed under the same license terms.
There are three sub-directories in this repository: one for the DE2-115, one for the DE0-Nano, and one for the BeMicroCV. They each contain an identical set of Verilog and AHDL files, along with unique .qsf and .cof files to differentiate the pinouts and programming images for the three different FPGA boards.
To compile for an FPGA board, go into the appropriate directory and follow the instructions in the readme or setup file. After compilation and download, the FPGA board will behave like a P8X32A Propeller chip, according to the pinout shown in the .png file. The emulated P8X32A chip will behave as if a 5MHz input is fed into the XI pin. This allows normal 80MHz operation when PLL16X is used. You can program the ‘chip’ via any Propeller development software (like Propeller Tool, PropellerIDE, or SimpleIDE) by plugging a Prop Plug into the pins outlined in the .png file.
The root directory contains the original .src files for the code in the P8X32A’s ROM. You must rename them to .spin files and put a ‘PUB anyname’ at their top before compiling them. They are not directly executable, but are provided to show you what went into the ROM:
To properly view the Verilog and AHDL source files, be sure to set the tab size to 4 spaces in Quartus II via: